2.3.6.3.1 Timing Characteristics

Table 2-72. Input Data Register Propagation Delays Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425 V
Parameter	Description	–1	Std.	Units
t_ICLKQ	Clock-to-Q of the Input Data Register	0.25	0.30	ns
t_ISUD	Data Setup Time for the Input Data Register	0.28	0.33	ns
t_IHD	Data Hold Time for the Input Data Register	0.00	0.00	ns
t_ISUE	Enable Setup Time for the Input Data Register	0.39	0.47	ns
t_IHE	Enable Hold Time for the Input Data Register	0.00	0.00	ns
t_ICLR2Q	Asynchronous Clear-to-Q of the Input Data Register	0.48	0.58	ns
t_IPRE2Q	Asynchronous Preset-to-Q of the Input Data Register	0.48	0.58	ns
t_IREMCLR	Asynchronous Clear Removal Time for the Input Data Register	0.00	0.00	ns
t_IRECCLR	Asynchronous Clear Recovery Time for the Input Data Register	0.24	0.28	ns
t_IREMPRE	Asynchronous Preset Removal Time for the Input Data Register	0.00	0.00	ns
t_IRECPRE	Asynchronous Preset Recovery Time for the Input Data Register	0.24	0.28	ns
t_IWCLR	Asynchronous Clear Minimum Pulse Width for the Input Data Register	0.22	0.26	ns
t_IWPRE	Asynchronous Preset Minimum Pulse Width for the Input Data Register	0.22	0.26	ns
t_ICKMPWH	Clock Minimum Pulse Width High for the Input Data Register	0.36	0.42	ns
t_ICKMPWL	Clock Minimum Pulse Width Low for the Input Data Register	0.32	0.38	ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.