2.3.6.5.1 Timing Characteristics

Table 2-74. Output Enable Register Propagation Delays Worst Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.425V
Parameter	Description	–1	Std.	Units
t_OECLKQ	Clock-to-Q of the Output Enable Register	0.47	0.56	ns
t_OESUD	Data Setup Time for the Output Enable Register	0.33	0.40	ns
t_OEHD	Data Hold Time for the Output Enable Register	0.00	0.00	ns
t_OESUE	Enable Setup Time for the Output Enable Register	0.46	0.55	ns
t_OEHE	Enable Hold Time for the Output Enable Register	0.00	0.00	ns
t_OECLR2Q	Asynchronous Clear-to-Q of the Output Enable Register	0.70	0.84	ns
t_OEPRE2Q	Asynchronous Preset-to-Q of the Output Enable Register	0.70	0.84	ns
t_OEREMCLR	Asynchronous Clear Removal Time for the Output Enable Register	0.00	0.00	ns
t_OERECCLR	Asynchronous Clear Recovery Time for the Output Enable Register	0.24	0.28	ns
t_OEREMPRE	Asynchronous Preset Removal Time for the Output Enable Register	0.00	0.00	ns
t_OERECPRE	Asynchronous Preset Recovery Time for the Output Enable Register	0.24	0.28	ns
t_OEWCLR	Asynchronous Clear Minimum Pulse Width for the Output Enable Register	0.22	0.26	ns
t_OEWPRE	Asynchronous Preset Minimum Pulse Width for the Output Enable Register	0.22	0.26	ns
t_OECKMPWH	Clock Minimum Pulse Width High for the Output Enable Register	0.36	0.42	ns
t_OECKMPWL	Clock Minimum Pulse Width Low for the Output Enable Register	0.32	0.38	ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.