2.3.6.4.1 Timing Characteristics

Table 2-73. Output Data Register Propagation Delays Worst Military-Case Conditions: T_J= 125 °C, Worst-Case VCC = 1.425V
Parameter	Description	–1	Std.	Units
t_OCLKQ	Clock-to-Q of the Output Data Register	0.62	0.75	ns
t_OSUD	Data Setup Time for the Output Data Register	0.33	0.40	ns
t_OHD	Data Hold Time for the Output Data Register	0.00	0.00	ns
t_OSUE	Enable Setup Time for the Output Data Register	0.46	0.56	ns
t_OHE	Enable Hold Time for the Output Data Register	0.00	0.00	ns
t_OCLR2Q	Asynchronous Clear-to-Q of the Output Data Register	0.85	1.02	ns
t_OPRE2Q	Asynchronous Preset-to-Q of the Output Data Register	0.85	1.02	ns
t_OREMCLR	Asynchronous Clear Removal Time for the Output Data Register	0.00	0.00	ns
t_ORECCLR	Asynchronous Clear Recovery Time for the Output Data Register	0.24	0.28	ns
t_OREMPRE	Asynchronous Preset Removal Time for the Output Data Register	0.00	0.00	ns
t_ORECPRE	Asynchronous Preset Recovery Time for the Output Data Register	0.24	0.28	ns
t_OWCLR	Asynchronous Clear Minimum Pulse Width for the Output Data Register	0.22	0.26	ns
t_OWPRE	Asynchronous Preset Minimum Pulse Width for the Output Data Register	0.22	0.26	ns
t_OCKMPWH	Clock Minimum Pulse Width High for the Output Data Register	0.36	0.42	ns
t_OCKMPWL	Clock Minimum Pulse Width Low for the Output Data Register	0.32	0.38	ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.