9.4.6.2 Voltage Monitor Status Register

Note:

The bit is hardware set at the end of the round-robin sequence and is hardware cleared half a clock cycle later (providing sufficient time to synchronize any updates before the next sequence).
Hardware sets the bit when a Reset request is made due to a Fault-injected condition.
Hardware sets the bit upon completion of the scan.

Name:	VM1STAT
Offset:	0x3B2C


Bit	31	30	29	28	27	26	25	24
	WRALLOW							FLTRST
Access	R/HS/HC							R/HS/HC
Reset	0							0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
				SCANSRC[3:0]				SCANBG
Access				R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset				0	0	0	0	0

Bit 31 – WRALLOW Configuration Write Allow Status bit⁽¹⁾

Value	Description
1	VMxCON[SCANPS[2:0]] and VMxFLT can be safely written without creating a false error event.
0	Writing to VMxCON[SCANPS[2:0]] and VMxFLT is not allowed; writing can cause unexpected behavior of the module or a false error event.

Bit 24 – FLTRST Power Monitor Reset Status bit⁽²⁾

Value	Description
1	Reset event caused by the module occurred while performing Fault injection.
0	No Reset event caused by Fault injection testing has occurred.

Bits 4:1 – SCANSRC[3:0] Factory Source Scanned Status bit

Value	Description
1000	VREG4 Scan is complete.
0100	VREG3 Scan is complete.
0010	VREG2 Scan is complete.
0001	V_DDCORE (Buck) scan is complete.
0000	No factory sources were scanned.

Bit 0 – SCANBG Bandgap Scan Status bit⁽³⁾

Value	Description
1	Bandgap scan is complete.
0	Bandgap has not been scanned.

DS70005629B

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