9.4.6.1 Voltage Monitor Control Register
Note:
- Bit can only be set by the user; setting the bit initiates a status register clearing sequence between the two clock domains.
- Bit is cleared by hardware once the status bits are cleared.
- Bit can only be set by the user.
- If FLTRSTEN =
1, the minimum value allowed to be written to this bit field is 0b001.
| Name: | VM1CON |
| Offset: | 0x3B28 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ON | |||||||||
| Access | R/S/HS | ||||||||
| Reset | x |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SCANPS[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLRSTAT | |||||||||
| Access | R/W/HC | ||||||||
| Reset | 0 |
Bit 31 – ON Power Monitor Enable bit(3)
| Value | Description |
|---|---|
| 1 | Power Monitor Module is enabled. |
| 0 | Power Monitor Module is not enabled. |
Bits 10:8 – SCANPS[2:0] Scan Postscaler bits(4)
| Value | Description |
|---|---|
| 111 | 16384x duration between scans |
| ... | |
| 010 | 16x duration between scans |
| 001 | 4x duration between scans |
| 000 | Back-to-back, continuous scan at maximum scan frequency (approx. 34 kHz scan rate for 5 inputs plus one extra pulse for WRALLOW using the 170 kHz internal clock) |
Bit 0 – CLRSTAT Status Clear Request bit(1,2)
| Value | Description |
|---|---|
| 1 | Request to clear status registers initiated. |
| 0 | No pending request to clear VMxSTAT or VMxEVENT registers |