17.4.8 Result

When each record is processed by the math sequencer, the math sequencer result can be stored as defined by Write mode bits WM[1:0] in the ITCLSxCON register. Also, ITCLSxCON WM[1:0] bits can be overwritten/replaced with other ITCSMATHCMDx WM[1:0] settings in the math sequencer command. These bits in the math command overwrite the list register settings WM[1:0] only when the WMOV bit = 1 in the math command. The following write result options are available:

• WM[1:0] = 0 means “always write.”
• WM[1:0] = 1 means that the math result is stored only when a comparator event is detected.
• WM[1:0] = 2 means “never write.”

For each record, each math sequencer command stores the result in the corresponding ITCRESx register as defined by the WM[1:0] bits. The data processed by the math sequencer can be in unsigned or signed formats. The format is selected by the SIGN bit in the ITCCON1 register. SIGN bit = 0 means unsigned, and SIGN bit = 1 means signed format. The CVD algorithm accumulates the difference between Sample A and B. In the case of CVD, the SIGN bit must always be set.

All data in the math sequencer are 24-bit in size. Bit 23 is a sign bit. When the math sequencer's signed result is stored into the 32-bit ITCRESx register, the sign bit is extended automatically.