17.4.18 Hardware Coded Sequences

Two sequences are predefined in the hardware.

When DATASEQ[2:0] bits = 0 in the ITCLSxSEQ register, the ITC module just converts the voltage on the ANx input. The accumulations when ACCNUM[7:0] bits are zero and comparison to the thresholds in the ITCLSxCMPLO and ITCLSxCMOHI registers can be enabled in the CM[2:0] bits of the ITCLSxCON register. The results are stored in the ITCRESx registers.

When DATASEQ[2:0] bits = 1 in the ITCLSxSEQ register, the ITC module executes a basic CVD procedure for ANx input (Sample A – Sample B). The software trigger (ITCLSxCON.TRGSRC[4:0] = 0) cannot be used to start CVD. The SAMP bit in the ITCLSxCON register must be zero when the CVD sequence is selected. The CVDTXx pins selected in the ITCTXA registers are toggled in phase with the charge and discharge levels of the sensor. The CVDTXx pins selected in the ITCTXB register are toggled opposite to the charge and discharge levels of the sensor. The accumulations are controlled by ACCNUM[7:0] bits, and comparison to the thresholds in the ITCLSxCMPLO and ITCLSxCMOHI registers can be enabled in the CM[2:0] bits of the ITCLSxCON register. The results are stored in the ITCRESx registers.