17.4.16 Acquisition Sequencer Commands
The acquisition sequence is executed each time the record is triggered.
The sequence is finished when the END bit is set.
The command can delay the execution as specified in the LOOP[3:0] bits.
Each acquisition sequence must call the math sequence. It is done if the MSTART bit is set in the command. The math sequence to be executed is specified by the MSEQ[3:0] bits of the acquisition command.
The CHOLD and CVD capacitors array, when the array is enabled, are controlled by the DISCHRG (discharge to VSS), CHRG (charge to VDD) and BAL (connect to ANx pin) bits.
When the BAL bit is set to connect the CHOLD and CVD capacitors to the CVDANx
pin, the four list timers in the ITCLSxTMR register can be used to provide a
sampling/settle delay required. The timer to wait is selected by the LOOP[3:0] bits. In
addition, the option LOOP[3:0] = 3 allows using the DLYCNT[4:0] bits in
the ITCLSxCON as a timer.
The CONV bit starts a conversion of an analog level on CHOLD (and CVD
capacitor, if enabled). The command can wait for the end of the conversion if LOOP[3:0]
bits = 4. The BAL bit must always be set when the conversion is started
(CONV bit = ‘1’).
The CVDANx pin is controlled by the PC0[1:0] bits. The following options are available:
0– The CVDANx pin is controlled by the corresponding TRIS and LAT bits.1– The CVDANx pin is driven to a low level.2– The CVDANx pin is driven to a high level.3– The CVDANx pin is tri-stated.
In addition, the acquisition command can control up to three CVDTXx pins. These pins can be used to implement the mutual capacitance low impedance signal or active guards.
The PCA[1:0] bits control CVDTXx pins assigned in the ITCTXA register.
The PCB[1:0] bits control CVDTXx pins assigned in the ITCTXB register.
The PCC[1:0] bits control CVDTXx pins assigned in the ITCTXC register.
The available options are the same as ANx pin control:
0– The CVDTXx pin is controlled by the corresponding TRIS and LAT bits.1– The CVDTXx pin is driven to a low level.2– The CVDTXx pin is driven to a high level.3– The CVDTXx pin is tri-stated.
The acquisition command may generate DMA triggers. The DMA triggers must be enabled in the ITCLSxCON register using the DMAEN bit. When the DMATXA bit is set, the command asserts a DMATXA trigger. By this request, the DMA must write into the ITCTXA register to clear the trigger. If this write is not done, the next DMA trigger will not be processed. When the DMATXB bit is set, the command asserts a DMATXB trigger. By this request, the DMA must write into the ITCTXB register to clear the trigger. If this write is not done, the next DMA trigger will not be processed. When the DMATXC bit is set, the command asserts a DMATXC trigger. By this request, the DMA must write into the ITCTXC register to clear the trigger. If this write is not done, the next DMA trigger will not be processed. When the DMASTP bit is set, the command asserts a DMASTP trigger. By this request, the DMA must write into any ITCSDATACMDx register to clear the trigger. If this write is not done, the next DMA trigger will not be processed. The DMASTP trigger allows overwriting the acquisition sequence commands on the fly. It allows using long frequencies which cannot fit in the 16 available command registers.
If the record processing should be done a few times (accumulated, as specified by the ACCNUM[7:0] bits in the ITCLSxSEQ register), the DMA triggers (DMATXA, DMATXB, DMATXC, and DMASTP) may be sent only when the last accumulation of the record is finished. When set, the DMALACC bit allows the trigger defined by the DMATXA, DMATXB, DMATXC or DMASTP bits only when the last accumulation is done.
The records in the list are processed/scanned one-by-one. When set, the DMALAST bit allows the generation of DMATXA, DMATXB, DMATXC or DMASTP triggers only when the list scan is complete (the sequence is executed for the last time for the list).