17.4.7 Sampling, Balance, Conversion and Sequencers Timing

The ITC, including the acquisition and math sequencers, runs from the ADC 3 T_AD clock. The typical ADC 3 clock frequency is 80 MHz. Therefore, each sequencer command takes 12.5 ns. The CVD charge balance time is controlled in the acquisition commands. Also, the DLYCNT[4:0] bits of the ITCLSxCON register can be used to define the balance delay in the ADC 3 T_AD steps (12.5 ns typical). The balance time is started using the BAL bit in the acquisition sequence command. The acquisition sequencer can wait until the time defined by the DLYCNT[4:0] bits has elapsed when LOOP[3:0] bits = 3 in the acquisition sequencer command. The conversion of an analog level on the internal CVD capacitors array is done by ADC 3. The ADC 3 conversion takes two T_AD cycles (or 25 ns typical). The conversion is triggered by the CONV bit in the acquisition sequence command. The command with the CONV bit set sends a trigger to ADC 3. The acquisition sequencer can wait until the conversion ends when LOOP[3:0] bits = 4 in the acquisition sequencer command.