17.4.17 Math Sequencer Commands
The math post processing sequence is called by an acquisition sequence. The internal structure of the math hardware is shown in Figure 17-10.
The sequence is finished when the END bit is set.
The arithmetic module has two inputs: AIN and BIN. For input A (AIN[1:0] bits), the following sources can be selected:
0= Zero1= Accumulator A2= Reserved3= Conversion Result
For input B (BIN[1:0] bits), the following sources can be selected:
0= ITCRESx register1= Accumulator B2= Reserved3= Conversion Result
The math sequence command executes a math operation as specified by the F[1:0] bits. The following options are available:
0= data from A input is copied to the math result.1= data from B input is copied to the math result.2= the math result is a sum of B and A inputs.3= the math result is a difference between B and A inputs.
The output of the math operation is stored in the ITCRESx register if it is defined by the WM[1:0] bits of the ITCLSxCON register or by the WM[1:0] bits in the ITCSMATHCMDx command when the WMOV bit is set. Also, the math result can be latched into two accumulators when the ACCA and/or ACCB bits are set.
Once the ACCCLR bit is set, Accumulator A and Accumulator B are reset to zero.
The FIRST bit of the math command can be used for the ITCRESx registers
reset/initialization. The FIRST bit allows setting the arithmetic module input B to zero
when the record is processed for the very first time in the list scan. When the FIRST
bit is set ('=1'), the input B is zero for the first record
accumulation regardless of the BIN[1:0] bits settings.
When the CMP bit is set, a comparison of the Accumulator A executes with the ITCLSxCMPHI and ITCLSxCMPLO thresholds as defined by the CM[2:0] bits in the ITCLSxCON register.
The math command can generate the interrupt when the INT bit is set
(='1').
The ACCCLR, CMP and INT bits can be enabled only when the math sequence is executed for
the last record accumulation in the list scan. To do this, the LAST bit must be set
(='1').
