3.4.3.8.2 ISB Mode

The cache can be operated in a streaming for FIFO mode. This is a prefetch that reads a 128-cache line from the NVM Flash and feeds the instruction fetch unit of the dsPIC33A. This mode must also use the parity bit on the 32-bit instruction data to be consistent. The parity bit will be inserted, and the stream buffer is written. The inserted parity bit will be passed to the dsPIC33A instruction fetch unit. The parity bit can be checked in streaming mode as it is passed to the dsPIC33A; however, the only action to take on a parity error is to set the error flag in the status and raise an error event.

There is also SFR-based access to the stream buffers in each of the 8 slices. There is odd parity on each of the 32-bit instructions and on the address registers.