3.4.3.8.1 Cache Mode

The instruction memory in the NVM Flash will insert odd parity on each of the 4 - 32-bit instructions held in a cache line (128 bit plus ECC parity).

Per instruction word parity bits will be encoded and inserted into the data going to the cache and will not be covered by the ECC parity. By placing the insertion of the per instruction parity in the NVM, the Flash panel will not be changed.

Once the per-word (instruction) parity is inserted into the 32-bit data, it will be stored in the Cache RAM (and ISB). The 33-bit instruction will be passed through the instruction fetch unit in the dsPIC33A. If a parity error is detected in the dsPIC® instruction fetch unit, it will kill the instruction.