24.4.4.5.4 I2C Private Write or Read Transfers

The I2C private write and read transfers are initiated on the bus based on the I3CxCMDQUE settings, as shown in Table 24-12.

Table 24-12. I2C Private Write or Read Transfers
Command AttributeBit FieldProgrammed ValueDescription

Transfer Command

CP

0

Indicates to the controller not to consider the CMD field.

CMD[14]

NA

This field is not applicable since the CP bit is set to 0.

CMD[13:7]

NA

This field is not applicable since the CP bit is set to 0.

DEV_INDX

DEV_INDX

Indicates the index of the device table, which consists of the target address to be targeted.

SPEED

0 or 1

Indicates to the controller that the transfer should go in I2C SDR mode. Values (I2C mode):

0x0: I2C Fm

0x1: I2C Fm+

SDAP

0 or 1

0: Indicates to consider the transmit data from the Transmit FIFO if RnW is set to 0.

1: Indicates the controller to consider the receive data if RnW is set to 1.

RnW (Read and

Write)

0 or 1

Transmit data from the command if RnW is set to 0.

1: Indicates the transfer is a read transfer.

0: Indicates the transfer is a write transfer.

PEC

0 or 1

Indicates whether Packet Error Check is enabled for Private SDR transfers.

1: PEC check is enabled.

0: PEC check is disabled.

Transfer Argument (SDAP=0)

DATA_LENGTH

0 - 65535

Indicates the transfer length of the transfer.

Short Data Argument (SDAP=1)

BYTE_STRB

0,1,3,7

Indicates that the respective data bytes of the Immediate command are valid.

Note: The I3CxDEVADDRTAB1LOC1[DEVICE] bit in the device address table pointed to by the ‘DEV_INDX’ field of the Transfer Command must be set to ‘1’ for the I2C private transfers. The controller uses the I2C protocol to initiate the I2C transfers for the Legacy I2C devices. To allow the priority for the IBI from the I3C devices, the controller can include the address header for the I2C private transfers by enabling the IBA bit in the ‘I3CxCTRL’ register.