24.4.4.5.3 I3C Private Write or Read Transfers

Figure 24-18. Private Transfer

The I3C private write and read transfers are initiated on the bus based on the I3CxCMDQUE and settings shown in Table 24-11.

Table 24-11. I3C Private Write or Read Transfers
Command AttributeBit FieldProgrammed ValueDescription

Transfer Command

CP

0

Indicates to the controller not to consider the CMD field.

CMD[14]

NA

This field is not applicable since the CP bit is set to 0.

CMD[13:7]

NA

This field is not applicable since the CP bit is set to 0.

DEV_INDX

DEV_INDX

Indicates the index of the device table, which consists of the target address to be targeted.

SPEED

0 to 4

Indicates to the controller that the transfer should proceed in SDR mode.

SDAP

0 or 1

1: Indicates the controller should consider the transmit data from the command if RnW is set to 0.

0: Indicates to consider the transmit data from the Transmit FIFO if RnW is set to 0.

RnW (Read and

Write)

0 or 1

1: Indicates the transfer is a read transfer.

0: Indicates the transfer is a write transfer.

Indicates whether Packet Error Check is enabled.

Enabled for private SDR transfers.

PEC

0 or 1

0: PEC check is disabled.

1: PEC check is enabled.

Transfer Argument (CMD_ATTR=0)

DATA_LENGTH

0 - 65535

Indicates the transfer length of the transfer.

Short Data Argument (CMD_ATTR=1)

BYTE_STRB

0,1,3,7

Indicates that the respective data bytes of the Immediate command are valid.

Note:
  1. To avoid the initial latencies of the transfer, the controller uses TXSTART/RXSTART in the I3CxBUFTHLD register before initiating the transfer. TXSTART ensures the threshold level of data is present in the Transmit buffer for write transfer, and RXSTART ensures the level of space is available in the Receive buffer for the Read transfer before initiating the transfer. This threshold is only applicable for the transfers that are initiated with the START condition and not applicable for the transfers that are initiated with the RESTART condition for SDR Transfers.
  2. To allow priority for IBI from the devices, the controller can include the Address header for the I3C private transfers by enabling the IBA bit in the ‘I3CxCTRL’ register, since IBI always wins when arbitrated with the Address header.

The controller halts in the following conditions:

  • Receiving a NACK for the address header of the private transfers if the I3CxCTRL[IBA] bit is enabled.
  • Receiving a NACK for the target address of the private transfers.

The controller updates the ‘ERR_STS’ field with appropriate error information in the response status (I3CxRESPQUE), halts the controller, and returns control to the application to resume the operation of the controller by writing ‘1’ to the I3CxCTRL [RESUME] bit.