20.4.3.1 Hall Mode Operation

The Hall Operating mode is selected by writing HALLEN= 1 and CCM[1:0] = 00 in the QEIxCON register.

In Hall Operation mode, control logic QEA, QEB and QEC inputs represent the phase A, B and C of a Hall sensor, respectively. The three of Hall inputs (QEC, QEB, QEA) define the current Hall state. The six possible states are 3’b001, 3’b011, 3’b010, 3’b110, 3’b100 and 3’b101. By comparing the current state of the inputs with the previous state of the inputs, the direction and count status can be decoded.

Negative Rotation (Default): CBA=100 → 110 - 010 - 011- 001 - 101

Positive Rotation (Default): CBA=100 - 101 - 001 - 011- 010 -110

Table 20-3 shows the truth table that describes how the Hall sensor signals are decoded. Count pulses are generated when the Hall state changes. The Count direction is determined by the direction of the state changes.

The Hall filter checks for the valid Hall value. If an invalid Hall code is detected (000 or 111), the Hall state error interrupt flag, HSERRIRQ, will be set in the QEIx Status register (QEIxSTAT[19]). If HSERRIEN bit in the QEIx Status register is set (QEIxSTAT[18]), then an interrupt will be generated.

The Hall filter state match function can be enabled using HMATCHEN bit in the QEIxCON register. The user can configure the required Hall filter state match using the HMATCH[2:0] bits in the QEIxCON register. When the Hall filter state matches the HMATCH bits, the error interrupt flag, HSTAMIRQ, will be set in the QEIx Status register (QEIxSTAT[23]). If HSTAMIEN bit in QEIx status register is set (QEIxSTAT[22]), an interrupt will be generated.

Optionally, the programmable delay counter can be used to generate an interrupt after a programmable delay time. The delay time must be written in the Programmable Delay Compare register (QEIxHPDLY). The delay counter starts counting when the HMATCH[2:0] matches the Hall input code, and only if the respective HMATCH[2:0] value is different from zero. The HPDLYIRQ Interrupt Flag is generated when the delay counter reaches the QEIxHPDLY value. If HPDLYIEN bit in QEIx Status register is set (QEIxSTAT[24]), an interrupt will be generated.

The Position Counter (POSxCNT) starts incrementing/decrementing when a new Hall state transition is detected. The value of the counter is constantly monitored to detect error conditions. The window monitor lower threshold is defined by the Compare Low register (QEIxLEC), and the upper threshold value is defined by the Compare High register (QEIxGEC). If a Hall transition is detected and the counter is outside the window thresholds, error interrupt flags are set. The window upper threshold error status bit, PCHEQIRQ, in the QEIx Status register (QEIxSTAT[13]) is set, if the counter value is higher than QEIxGEC. If the PCHEQIEN bit in QEIx Status register (QEIxSTAT[12]) is set, an interrupt will be generated. The window lower threshold error status bit, PCLEQIRQ, in the QEIx Status register (QEIxSTAT[11]) is set, if the counter value is lower than QEIxLEC. If the PCLEQIEN bit in the QEIx Status register (QEIxSTAT[10]) is set, then an interrupt will be generated.