14.4.16 CAN Bus Diagnostics
Register 1
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxBDIAG1T: Accesses
the top byte BDIAG1[31:24]
- CxBDIAG1U: Accesses
the upper byte BDIAG1[23:16]
- CxBDIAG1: Accesses
the byte BDIAG1[31:0]
| Name: | C1BDIAG1 |
| Offset: | 0x263C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | DLCMM | ESI | DCRCERR | DSTUFERR | DFORMERR | | DBIT1ERR | DBIT0ERR | |
| Access | R/W | R/W | R/W | R/W | R/W | | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | TXBOERR | | NCRCERR | NSTUFERR | NFORMERR | NACKERR | NBIT1ERR | NBIT0ERR | |
| Access | R/W | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | EFMSGCNT[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | EFMSGCNT[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – DLCMM DLC Mismatch
bit
During a
transmission or reception, the specified DLC is larger than the PLSIZEx of the FIFO
element.
Bit 30 – ESI ESI Flag of
Received CAN FD Message Set bit
Bit 29 – DCRCERR Received Message
with CRC Incorrect Checksum in the Data Segment bit
The CRC Checksum of a received
message is considered incorrect if the CRC of the incoming message does not match
with the CRC calculated from the received data.
Bit 28 – DSTUFERR Received Message
with Illegal Sequence in the Data Segment bit
An Illegal Sequence occurs
when more than five equal bits appear in sequence in a part of the received message
where this is not allowed.
Bit 27 – DFORMERR Received Frame with
a Fixed Format Error in Data Segment bit
A fixed format error occurs
when a part of the incoming frame with a fixed format has the wrong
format.
Bit 25 – DBIT1ERR Transmitted Message
Recessive Level in Data Segment bit
During the data segment of a
message transmission, the device wanted to send a recessive level (bit of logical
value ‘1’), but the monitored bus value was
dominant.
Bit 24 – DBIT0ERR Transmitted Message
Dominant Level in Data Segment bit
During the transmission of a
message, the device wanted to send a dominant level (logical value
‘0’), but the monitored bus value was
recessive.
Bit 23 – TXBOERR Device Went to Bus
Off bit
Bit 21 – NCRCERR Received Message
with CRC Incorrect Checksum in Non-Data Segment bit
The CRC checksum of a received
message is considered incorrect if the CRC of the incoming message does not match
the CRC calculated from the received data.
Bit 20 – NSTUFERR Received Message
with Illegal Sequence in Non-Data Segment bit
An Illegal Sequence occurs
when more than five equal bits appear in sequence in a part of the received message
where this is not allowed.
Bit 19 – NFORMERR Received Frame with
a Fixed Format Error in Non-Data Segment bit
A fixed format error occurs
when a part of the incoming frame with a fixed format has the wrong
format.
Bit 18 – NACKERR Transmitted Message
Not Acknowledged bit
Transmitted message was not
Acknowledged.
Bit 17 – NBIT1ERR Transmitted Message
Dominant Level in Non-Data Segment bit
During the non-data segment of
a message transmission, the device wanted to send a recessive level (bit of logical
value ‘1’), but the monitored bus value was
dominant.
Bit 16 – NBIT0ERR Transmitted Message
Dominant Level in Non-Data Segment bit
During the transmission of a
message (or Acknowledge bit, or active error flag, or overload flag), the device
wanted to send a dominant level (logical value ‘0’), but the
monitored bus value was recessive. During bus-off recovery, this status is set each
time a sequence of 11 recessive bits has been monitored. This enables the CPU to
monitor the progress of the bus-off recovery sequence (indicating the bus is not
stuck at dominant or continuously disturbed).
Bits 15:0 – EFMSGCNT[15:0] Error-Free Message
Counter bits
