16.3.37 ADC 3 Channel n Counter Register

Legend: n = ADC channel number (0-11); HS = Hardware Settable bit; HC = Hardware Clearable bit; R = Readable bit

Name:	AD3CHnCNT
Offset:	0xAA8, 0xAC8, 0xAE8, 0xB08, 0xB28, 0xB48, 0xB68, 0xB88, 0xBA8, 0xBC8, 0xBE8, 0xC08


Bit	31	30	29	28	27	26	25	24
	CNTSTAT[15:8]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CNTSTAT[7:0]
Access	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R	HS/HC/R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – CNTSTAT[15:0] Count Status bits

Number of conversions done in integration (MODE[1:0] bits = ‘10’) and window (MODE[1:0] bits = ‘01’) sampling modes.

Bits 15:0 – CNT[15:0] Count bits

Number of samples for an integration sampling mode (MODE[1:0] bits = ‘10’) and the maximum number of samples for a window sampling mode (MODE[1:0] bits = ‘01’).