1 Device Overview

Note:
  1. This data sheet summarizes the features of the dsPIC33CK256MC006 family of devices. It is not intended to be a comprehensive resource. To complement the information in this data sheet, refer to the related section of the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip website (www.microchip.com).
  2. Some registers and associated bits described in this section may not be available on all devices. Refer to Memory Organization in this data sheet for device-specific register and bit information.

This document contains device-specific information for the dsPIC33CK256MC006 Digital Signal Controller (DSC) devices.

dsPIC33CK256MC006 devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit MCU architecture.

Figure 1-1 shows a general block diagram of the core and peripheral modules of the dsPIC33CK256MC006 family.

Figure 1-1. dsPIC33CK256MC006 Family Block Diagram(1)

Note:
  1. The numbers in the parentheses are the number of instantiations of the module indicated.
  2. Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count.
  3. Some peripheral I/Os are only accessible through Peripheral Pin Select (PPS).
Table 1-1. Pinout I/O Descriptions
Pin Name(1)Pin

Type

Buffer

Type

PPSDescription

AN0-AN19

ANN0

I

I


Analog

Analog

No

No

Analog input channels

Analog negative input

ADCTRG

I

ST

Yes

ADC Trigger Input 31

CAN1RX

CAN1TX

I

O

ST

—

Yes

Yes

CAN1 receive input

CAN1 transmit output

CLKI

CLKO

I

O

ST/CMOS

—

No

No

External Clock (EC) source input. Always associated with OSCI pin 
function.

Oscillator crystal output. Connects to a crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with the OSCO pin function.

OSCI

OSCO

I

I/O

ST/CMOS

—

No

No

Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

Oscillator crystal output. Connects to a crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

REFCLKIISTYesReference clock input
REFCLKOO—YesReference clock output

INT0

INT1

INT2

INT3

I

I

I

I

ST

ST

ST

ST

No

Yes

Yes

Yes

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

IOCA[4:0]

IOCB[15:0]

IOCC[15:0]

IOCD[15:0]

I

I

I

I

ST

ST

ST

ST

No

No

No

No

Interrupt-on-Change input for PORTA

Interrupt-on-Change input for PORTB

Interrupt-on-Change input for PORTC

Interrupt-on-Change input for PORTD

RA0-RA4

I/O

ST

No

PORTA is a bidirectional I/O port

RB0-RB15

I/O

ST

No

PORTB is a bidirectional I/O port

RC0-RC15

I/O

ST

No

PORTC is a bidirectional I/O port

RD0-RD15

I/O

ST

No

PORTD is a bidirectional I/O port

T1CK

I

ST

Yes

Timer1 external clock input

U1CTS

U1RTS

U1RX

U1TX

U1DSR

U1DTR

I

O

I

O

I

O

ST

—

ST

—

ST

—

Yes

Yes

Yes

Yes

Yes

Yes

UART1 Clear-to-Send

UART1 Request-to-Send

UART1 Receive

UART1 Transmit

UART1 Data-Set-Ready

UART1 Data-Terminal-Ready

U2CTS

U2RTS

U2RX

U2TX

U2DSR

U2DTR

I

O

I

O

I

O

ST

—

ST

—

ST

—

Yes

Yes

Yes

Yes

Yes

Yes

UART2 Clear-to-Send

UART2 Request-to-Send

UART2 Receive

UART2 Transmit

UART2 Data-Set-Ready

UART2 Data-Terminal-Ready

U3CTS

U3RTS

U3RX

U3TX

U3DSR

U3DTR

I

O

I

O

I

O

ST

—

ST

—

ST

—

Yes

Yes

Yes

Yes

Yes

Yes

UART3 Clear-to-Send

UART3 Request-to-Send

UART3 Receive

UART3 Transmit

UART3 Data-Set-Ready

UART3 Data-Terminal-Ready

SENT1

SENT1OUT

I

O

ST

—

Yes

Yes

SENT1 input

SENT1 output

PTGTRG24

PTGTRG25

O

O

—

—

Yes

Yes

PTG Trigger Output 24

PTG Trigger Output 25

TCKI1-TCKI4

ICM1-ICM4

OCFA-OCFD

OCM1-OCM4

I

I

I

O

ST

ST

ST

—

Yes

Yes

Yes

Yes

SCCP Timer Inputs 1 through 4

SCCP Capture Inputs 1 through 4

SCCP Fault Inputs A through D

SCCP Compare Outputs 1 through 4

SCK1

SDI1

SDO1

SS1

I/O

I

O

I/O

ST

ST

—

ST

Yes

Yes

Yes

Yes

Synchronous serial clock input/output for SPI1

SPI1 data in

SPI1 data out

SPI1 Client synchronization or frame pulse I/O

SCK2

SDI2

SDO2

SS2

I/O

I

O

I/O

ST

ST

—

ST

Yes

Yes

Yes

Yes

Synchronous serial clock input/output for SPI2

SPI2 data in

SPI2 data out

SPI2 Client synchronization or frame pulse I/O

SCL1

SDA1

ASCL1

ASDA1

I/O

I/O

I/O

I/O

ST

ST

ST

ST

No

No

No

No

Synchronous serial clock I/O for I2C1

Synchronous serial data I/O for I2C1

Alternate synchronous serial clock I/O for I2C1

Alternate synchronous serial data I/O for I2C1

TMS

TCK

TDI

TDO

I

I

I

O

ST

ST

ST

—

No

No

No

No

JTAG Test mode select pin

JTAG test clock input pin

JTAG test data input pin

JTAG test data output pin

PCI8-PCI22

PWMEA-PWMED

PWM1L-PWM4L(2)

PWM1H-PWM4H(2)

I

O

O

O

ST

—

—

—

Yes

Yes

No

No

PWM Inputs 8 through 22

PWM Event Outputs A through D

PWM Low Outputs 1 through 4

PWM High Outputs 1 through 4

CLCINA-CLCIND

CLC1OUT-CLC4OUT

I

O

ST

—

Yes

Yes

CLC Inputs A through D

CLC Outputs 1 through 4

CMP1

CMP1A

CMP1B

CMP1C

CMP1D

O

I

I

I

I

—

Analog

Analog

Analog

Analog

Yes

No

No

No

No

Comparator 1 output

Comparator Channel 1A input

Comparator Channel 1B input

Comparator Channel 1C input

Comparator Channels 1D input

PGD1

PGC1

PGD2

PGC2

PGD3

PGC3

I/O

I

I/O

I

I/O

I

ST

ST

ST

ST

ST

ST

No

No

No

No

No

No

Data I/O pin for Programming/Debugging Communication Channel 1

Clock input pin for Programming/Debugging Communication Channel 1

Data I/O pin for Programming/Debugging Communication Channel 2

Clock input pin for Programming/Debugging Communication Channel 2

Data I/O pin for Programming/Debugging Communication Channel 3

Clock input pin for Programming/Debugging Communication Channel 3

MCLR

I/P

ST

No

Master Clear (Reset) input. This pin is an active-low Reset to the device.

AVDD

P

P

No

Positive supply for analog modules. This pin must be connected at all times.

AVSS

P

P

No

Ground reference for analog modules. This pin must be connected at all times.

VDD

P

—

No

Positive supply for peripheral logic and I/O pins. This pin must be connected at all times.

VSS

P

—

No

Ground reference for logic and I/O pins. This pin must be connected at all times.

Legend:
  • CMOS = CMOS compatible input or output
  • Analog = Analog input
  • P = Power
  • ST = Schmitt Trigger input with CMOS levels
  • O = Output
  • I = Input
  • PPS = Peripheral Pin Select
  • TTL = TTL input buffer
Note:
  1. Not all pins are available in all package variants. See the Pin Diagrams section for pin availability.
  2. PWM4L and PWM4H pins are available on PPS.