16 Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) module is a synchronous serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SPI module is compatible with the Motorola^® SPI and SIOP interfaces. All devices in the dsPIC33CK256MC006 family include two SPI modules.

On 48-pin and 64-pin devices, the SPI instance, SPI2, can operate at higher speeds when selected as a non-PPS pin. The selection is done using the SPI2PIN bit (FDEVOPT[13]). If the bit for SPI2PIN is ‘1’, the PPS pin will be used. When SPI2PIN is ‘0’, the SPI signals are routed to dedicated pins.

The module supports operation in two Buffer modes. In Standard Buffer mode, data are shifted through a single serial buffer. In Enhanced Buffer mode, data are shifted through a FIFO buffer. The FIFO level depends on the configured mode.

Variable length data can be transmitted and received, ranging from 2 to 32 bits.

The module also supports a basic framed SPI protocol while operating in either Host or Client mode. A total of four framed SPI configurations are supported.

The module also supports Audio modes. Four different Audio modes are available.

• I²S mode
• Left Justified mode
• Right Justified mode
• PCM/DSP mode

If an audio protocol data transfer takes place between two devices, one device is usually the Host and the other is the Client. However, audio data can be transferred between two Clients. Because the audio protocols require free-running clocks, the Host can be a third-party controller. In either case, the Host generates two free-running clocks: SCKx and LRC (Left, Right Channel Clock/SSx/FSYNC). In each of these modes, the serial clock is free-running and audio data are always transferred.

The SPI serial interface consists of four pins:

• SDIx: Serial Data Input
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
• SSx: Active-Low Client Select or Frame Synchronization I/O Pulse

The SPI module can be configured to operate using two, three or four pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used.

The SPI module has the ability to generate three interrupts, reflecting the events that occur during the data communication. The following types of interrupts can be generated:

1. Receive interrupts are signaled by SPIxRXIF. This event occurs when:
   • RX watermark interrupt
   • SPIROV = 1
   • SPIRBF = 1
   • SPIRBE = 1

   provided the respective mask bits are enabled in SPIxIMSKL/H.

2. Transmit interrupts are signaled by SPIxTXIF. This event occurs when:
   • TX watermark interrupt
   • SPITUR = 1
   • SPITBF = 1
   • SPITBE = 1

   provided the respective mask bits are enabled in SPIxIMSKL/H.

3. General interrupts are signaled by SPIxGIF. This event occurs when:
   • FRMERR = 1
   • SPIBUSY = 1
   • SRMT = 1

   provided the respective mask bits are enabled in SPIxIMSKL/H.

Block diagrams of the module in Standard and Enhanced modes are shown in Figure 16-1 and Figure 16-2.

To set up the SPIx module for the Standard Host mode of operation:

1. If using interrupts:
   1. Clear the interrupt flag bits in the respective IFSx register.
   2. Set the interrupt enable bits in the respective IECx register.
   3. Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
2. Write the desired settings to the SPIxCON1L and SPIxCON1H registers with the MSTEN bit (SPIxCON1L[5]) = 1.
3. Clear the SPIROV bit (SPIxSTATL[6]).
4. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
5. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data are written to the SPIxBUFL and SPIxBUFH registers.

To set up the SPIx module for the Standard Client mode of operation:

1. Clear the SPIxBUF registers.
2. If using interrupts:
   1. Clear the SPIxBUFL and SPIxBUFH registers.
   2. Set the interrupt enable bits in the respective IECx register.
   3. Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with the MSTEN bit (SPIxCON1L[5]) = 0.
4. Clear the SMP bit.
5. If the CKE bit (SPIxCON1L[8]) is set, then the SSEN bit (SPIxCON1L[7]) must be set to enable the SSx pin.
6. Clear the SPIROV bit (SPIxSTATL[6]).
7. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).

To set up the SPIx module for the Enhanced Buffer Host mode of operation:

1. If using interrupts:
   1. Clear the interrupt flag bits in the respective IFSx register.
   2. Set the interrupt enable bits in the respective IECx register.
   3. Write the SPIxIP bits in the respective IPCx register.
2. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with MSTEN (SPIxCON1L[5]) = 1.
3. Clear the SPIROV bit (SPIxSTATL[6]).
4. Select Enhanced Buffer mode by setting the ENHBUF bit (SPIxCON1L[0]).
5. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
6. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data are written to the SPIxBUFL and SPIxBUFH registers.

To set up the SPIx module for the Enhanced Buffer Client mode of operation:

1. Clear the SPIxBUFL and SPIxBUFH registers.
2. If using interrupts:

   Clear the interrupt flag bits in the respective IFSx register.

   Set the interrupt enable bits in the respective IECx register.

   Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.

3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with the MSTEN bit (SPIxCON1L[5]) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx pin.
6. Clear the SPIROV bit (SPIxSTATL[6]).
7. Select Enhanced Buffer mode by setting the ENHBUF bit (SPIxCON1L[0]).
8. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).

To set up the SPIx module for Audio mode:

1. Clear the SPIxBUFL and SPIxBUFH registers.
2. If using interrupts:
   1. Clear the interrupt flag bits in the respective IFSx register.
   2. Set the interrupt enable bits in the 
respective IECx register.
   3. Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with AUDEN (SPIxCON1H[15]) = 1.
4. Clear the SPIROV bit (SPIxSTATL[6]).
5. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L[15]).
6. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data are written to the SPIxBUFL and SPIxBUFH registers.