26 Dual Watchdog Timer (WDT)

Note: This data sheet summarizes the features of the dsPIC33CK256MC006 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Dual Watchdog Timer”, (www.microchip.com/DS70005250) in the “dsPIC33/PIC24 Family Reference Manual”.

The dsPIC33 dual Watchdog Timer (WDT) is described in this section. Refer to Figure 26-1 for a block diagram of the WDT.

The WDT, when enabled, operates from the internal Low-Power RC (LPRC) Oscillator clock source or a selectable clock source in Run mode. The WDT can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. The WDT can be configured in Windowed mode or Non-Windowed mode. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode (Power Save mode). If the WDT expires and issues a device Reset, the WTDO bit in the RCON register will be set.

Note: Run mode WDT is made to stall during NVM operation whenever code execution and NVM operation happen on the same Flash partition, and it resumes its counter once after NVM programming.

The following are some of the key features of the WDT modules:

  • Configuration or Software Controlled
  • Separate User-Configurable Time-out Periods for Run and Sleep/Idle
  • Can Wake the Device from Sleep or Idle
  • User-Selectable Clock Source in Run Mode
  • Operates from LPRC in Sleep/Idle Mode
Figure 26-1. Watchdog Timer Block Diagram