Core: 16-Bit dsPIC33CK CPU

  • 32-256 Kbytes of Program Flash with ECC and 8K-16K Data RAM
  • Fast 6-Cycle Divide
  • Code Efficient (C and Assembly) Architecture
  • 40-Bit Wide Accumulators
  • Single-Cycle (MAC/MPY) with Dual Data Fetch
  • Single-Cycle, Mixed-Sign MUL Plus Hardware Divide
  • 32-Bit Multiply Support
  • Five Sets of Interrupt Context Selected Registers for Fast Interrupt Response
  • Zero-Overhead Looping
  • 384 Bytes of One-Time-Programmable (OTP) Memory