9 Oscillator with High-Frequency PLL

Note: This data sheet summarizes the features of the dsPIC33CK256MC006 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Oscillator Module with High-Speed PLL” (www.microchip.com/DS70005255) in the “dsPIC33/PIC24 Family Reference Manual”.

The dsPIC33CK256MC006 family oscillator with high-frequency PLL includes these characteristics:

  • On-Chip Phase-Locked Loop (PLL) to Boost Internal Operating Frequency on Select Internal and External Oscillator Sources
  • Doze mode for System Power Savings
  • Scalable Reference Clock Output (REFCLKO)
  • On-the-Fly Clock Switching between Various Clock Sources
  • Fail-Safe Clock Monitoring (FSCM) that Detects Clock Failure and Permits Safe Application Recovery or Shutdown

A block diagram of the dsPIC33CK256MC006 oscillator system is shown in Figure 9-1.

Figure 9-1. dsPIC33CK256MC006 Core Clock Sources Block Diagram
Figure 9-2. dsPIC33CK256MC006 Oscillator Subsystem
Note:
  1. See Figure 9-3 for details of the PLL module.
  2. See Figure 9-3 for the source of FVCO.
  3. XTPLL, HSPLL, ECPLL, FRCPLL.
  4. Clock option for PWM.
  5. Clock option for ADC.
  6. Clock option for DAC.
  7. Clock option for UART.
  8. Clock option for REFO.
  9. Clock option for PTG.