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16-Bit Digital Signal Controllers with High-Speed PWM and CAN Flexible Data-Rate (CAN FD)
Operating Conditions
Core: 16-Bit dsPIC33CK CPU
Clock Management
Power Management
High-Speed PWM
Timers/Output Compare/Input Capture
Advanced Analog Features
Communication Interfaces
Direct Memory Access (DMA)
Peripheral Features
Debugger Development Support
Safety Features
Qualification Support
dsPIC33CK256MC006 Product Families
Pin Diagrams
Pin Diagrams (Continued)
Pin Diagrams (Continued)
Pin Diagrams (Continued)
1 Device Overview
2 Guidelines for Getting Started with 16-Bit Digital Signal Controllers
2.1 Basic Connection Requirements
2.2 Decoupling Capacitors
2.3 Master Clear (MCLR) Pin
2.4 ICSP Pins
2.5 External Oscillator Pins
2.6 External Oscillator Layout Guidance
2.7 Oscillator Value Conditions on Device Start-up
2.8 Unused I/Os
2.9 Bulk Capacitors
2.10 Targeted Applications
3 CPU
3.1 Registers
3.2 Instruction Set
3.3 Data Space Addressing
3.4 Addressing Modes
3.5 CPU Control/Status Registers
3.6 Arithmetic Logic Unit (ALU)
3.7 DSP Engine
4 Memory Organization
4.1 Program Address Space
4.2 Data Address Space
4.3 BIST Overview
4.4 Memory Resources
4.5 Bit-Reversed Addressing
4.6 Interfacing Program and Data Memory Spaces
5 Flash Program Memory
5.1 Table Instructions and Flash Programming
5.2 RTSP Operation
5.3 Error Correcting Code (ECC)
5.4 ECC Fault Injection
5.5 Flash OTP by ICSP™ Write Inhibit
5.6 Program Flash Memory Control Registers
5.7 ECC Control Registers
6 Resets
6.1 Reset Resources
6.2 Reset Control Register
Reset Control Register
6.3 Key Resources
7 Interrupt Controller
7.1 Interrupt Vector Table
7.2 Alternate Interrupt Vector Table
7.3 Reset Sequence
7.4 Interrupt Resources
7.5 Interrupt Control and Status Registers
7.6 INTCON1 through INTCON4
7.7 Status/Control Registers
7.8 Key Resources
8 I/O Ports
8.1 Parallel I/O (PIO) Ports
8.2 Configuring Analog and Digital Port Pins
8.3 Input Change Notification (ICN)
8.4 Peripheral Pin Select (PPS)
8.5 Considerations for Peripheral Pin Selection
8.6 Input Mapping
8.7 Virtual Connections
8.8 Output Mapping
8.9 Mapping Limitations
8.10 I/O Helpful Tips
8.11 I/O Ports Resources
9 Oscillator with High-Frequency PLL
9.1 Primary PLL
9.2 CPU Clocking
9.3 Primary Oscillator (POSC)
9.4 Internal Fast RC (FRC) Oscillator
9.5 Low-Power RC (LPRC) Oscillator
9.6 Internal Backup Fast RC (BFRC) Oscillator
9.7 Reference Clock Output
9.8 Oscillator Configuration
9.9 OSCCON Unlock Sequence
9.10 Oscillator Control Registers
10 Direct Memory Access (DMA) Controller
10.1 Summary of DMA Operations
10.2 Typical Setup
11 Controller Area Network Flexible Data-Rate (CAN FD) Modules
11.1 Features
11.2 CAN Control/Status Registers
12 High-Speed PWM
12.1 Features
12.2 Architecture Overview
12.3 Lock and Write Restrictions
12.4 PWM4H/L Output on Peripheral Pin Select
12.5 PWM Control/Status Registers
12.6 Control Registers
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13 High-Speed, 12-Bit Analog-to-Digital Converter
13.1 ADC Features Overview
13.2 Analog-to-Digital Converter Resources
13.3 ADC Control Registers
14 High-Speed Analog Comparator with Slope Compensation DAC
14.1 Overview
14.2 Features Overview
14.3 DAC Control Registers
14.4 DAC Control Registers
15 Universal Asynchronous Receiver Transmitter (UART)
15.1 Architectural Overview
15.2 Character Frame
15.3 Data Buffers
15.4 Protocol Extensions
15.5 UART Control/Status Registers
16 Serial Peripheral Interface (SPI)
16.1 SPI Control/Status Registers
17 Inter-Integrated Circuit (I2C)
17.1 Communicating as a Host in a Single Host Environment
17.2 Setting Baud Rate When Operating as a Bus Main
17.3 Secondary Address Masking
17.4 SMBus Support
17.5 I2C Control/Status Registers
18 Single-Edge Nibble Transmission (SENT)
18.1 Transmit Mode
18.2 Receive Mode
18.3 SENT Control/Status Registers
19 Timer1
19.1 Timer1 Control Registers
20 Capture/Compare/PWM/Timer Modules (SCCP)
20.1 Time Base Generator
20.2 General Purpose Timer
20.3 Output Compare Mode
20.4 Input Capture Mode
20.5 Auxiliary Output
20.6 SCCP Control/Status Registers
21 Configurable Logic Cell (CLC)
21.1 Control Registers
21.2 CLC Control Registers
22 Peripheral Trigger Generator (PTG)
22.1 Features
22.2 PTG Registers
22.3 PTG Step Commands
23 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
23.1 CRC Control Registers
24 Deadman Timer (DMT)
24.1 Deadman Timer Control/Status Registers
25 Power-Saving Features
25.1 Clock Frequency and Clock Switching
25.2 Instruction-Based Power-Saving Modes
25.3 Interrupts Coincident with Power Save Instructions
25.4 Doze Mode
25.5 Peripheral Module Disable
25.6 Power-Saving Control Registers
25.7 Power-Saving Resources
26 Dual Watchdog Timer (WDT)
26.1 Watchdog Timer Control Register Low
Watchdog Timer Control Register Low
26.2 Watchdog Timer Control Register High
Watchdog Timer Control Register High
27 Special Features
27.1 Configuration Bits
27.2 Configuration Registers
27.3 Device Calibration and Identification
27.4 User OTP Memory
27.5 On-Chip Voltage Regulator
27.6 Brown-out Reset (BOR)
27.7 JTAG Interface
27.8 In-Circuit Serial Programming™ (ICSP™)
27.9 In-Circuit Debugger
27.10 Code Protection and CodeGuard™ Security
28 Instruction Set Summary
29 Development Support
30 Electrical Characteristics
30.1 DC Characteristics
30.2 AC Characteristics and Timing Parameters
31 Packaging Information
31.1 Package Marking Information
31.2 Package Details
32 Revision History
33 Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

DS70005633B

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