10.7.4 Interrupt Flags

Note: This register has no accompanying INTCTRL register since all flags are registered as NMIs, which are always enabled. It is possible to prevent these interrupts by setting the Disable NMI Request (NMIDIS) bit in the Control A (CTRLA) register to DISABLED.

Note: This register is under Configuration Change Protection since the interrupt flags may indicate a hardware error and are considered more severe than ordinary interrupt flags.

Name:	INTFLAGS
Offset:	0x6
Reset:	0xXX
Property:	Configuration Change Protection


Bit	7	6	5	4	3	2	1	0
				PARITYI	PARITYD	SPLIM	BUSERR	OPC
Access				R/W	R/W	R/W	R/W	R/W
Reset				x	x	x	x	x

Bit 4 – PARITYI Parity Error on Instruction Bus

This flag is set when a parity error is detected in an instruction read on the instruction bus.

Write this bit to ‘1’ to clear the flag.

The CPU interrupt request will be asserted when this flag is set.

Bit 3 – PARITYD Parity Error on Data Bus

This flag is set when a parity error is detected in the data read on the data bus. PARITYD is also set on parity errors on the bus that addresses the single-cycle I/O registers (first 64 address locations).

Write this bit to ‘1’ to clear the flag.

The CPU interrupt request will be asserted when this flag is set.

Bit 2 – SPLIM Stack Pointer Limit Error

This flag is set when the stack pointer limit is exceeded. In other words, when the stack has overflowed or underflowed.

Write this bit to ‘1’ to clear the flag.

The CPU interrupt request will be asserted when this flag is set.

Bit 1 – BUSERR Bus Error

This flag is set when the bus target returns a bus target error signal on the bus. This error signal is triggered by an illegal address, parity error or other target-dependent error.

Write this bit to ‘1’ to clear the flag.

The CPU interrupt request will be asserted when this flag is set.

Bit 0 – OPC Illegal Opcode Error

This flag is set when an illegal opcode has been fetched and decoded.

Write this bit to ‘1’ to clear the flag.

The CPU interrupt request will be asserted when this flag is set.

This register has no accompanying INTCTRL register since all flags are registered as NMIs, which are always enabled. It is possible to prevent these interrupts by setting the Disable NMI Request (NMIDIS) bit in the Control A (CTRLA) register to DISABLED.This register is under Configuration Change Protection since the interrupt flags may indicate a hardware error and are considered more severe than ordinary interrupt flags.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.