10.7.6 Status Register
The Status Register contains information about the result of the most recently executed arithmetic or logic instructions. See the Instruction Set Summary section for the bit details in this register and how they are influenced by different instructions.
| Name: | SREG |
| Offset: | 0xF |
| Reset: | 0x0 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| I | T | H | S | V | N | Z | C | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – I Global Interrupt Enable
Writing a ‘1’ to this bit enables interrupts on the device.
Writing a ‘0’ to this bit disables the interrupts on the device,
independent of the individual interrupt enable settings of the peripherals.
This bit is not cleared by hardware while entering an Interrupt Service Routine (ISR) or
set when the RETI instruction is executed.
This bit can be set and cleared by software with the SEI and
CLI instructions.
Changing the I bit through the I/O register results in a one-cycle wait state on the access.
Bit 6 – T Bit Copy Storage
The bit copy instructions, Bit Load (BLD) and Bit Store
(BST), use the T bit as the source or destination for the operated
bit.
A bit from a register in the register file can be copied into this bit by the
BST instruction, and this bit can be copied into a bit in a register in
the register file by the BLD instruction.