10.7.5 Stack Pointer
This register holds the Stack Pointer (SP) that points to the top of the stack. After being reset, the SP points to the highest internal SRAM address.
Only the number of bits required to address the available SRAM is implemented for each
device. Unused bits will always read as ‘0’.
The SPL and SPH register pair represents the 16-bit value SP. The low byte [7:0] (suffix L)
is accessible at the original offset. This high byte [15:8] (suffix H) can be accessed at
offset + 0x01.
To prevent corruption when updating the SP from software, a write to SPL will automatically disable interrupts for the following four instructions or until the next I/O memory write, whichever comes first.
| Name: | SP |
| Offset: | 0xD |
| Reset: | 0x7FFF |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |