10.7.3 Control A
| Name: | CTRLA |
| Offset: | 0x5 |
| Reset: | 0x0 |
| Property: | Configuration Change
Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | NMIDIS | INJCOMP | INJPDD | INJPDA | INJPDC | INJPIA | INJPIC | SPLOCK | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – NMIDIS Disable NMI
Request
This bit will disable any
Non-Maskable Interrupt (NMI) during error injection, so that any error injection that will
set a flag in CPU.INTFLAGS does not trigger an NMI.
| Value | Name | Description |
|---|
| 0x0 |
ENABLED |
NMI is
enabled |
| 0x1 |
DISABLED |
NMI is
disabled |
Bit 6 – INJCOMP Inject Comparator Error
Write this bit to
‘1’ to inject a compare error in the lockstep comparator. This bit is
automatically cleared by HW after one instruction has completed.
Bit 5 – INJPDD Inject Parity Error on Data Bus Data
Write this bit to
‘1’ to inject a parity error in the data on the following data bus write
access. This bit is automatically cleared after one access is completed. Parity errors will
be injected only on main data bus accesses, not on accesses to the bus that address the
single-cycle I/O registers (first 64 address locations).
Bit 4 – INJPDA Inject Parity Error on Data Bus Address
Write this bit to
‘1’ to inject a parity error in the address on the following data bus
access. This bit is automatically cleared after one access is completed. Parity errors will
be injected only on main data bus accesses, not on accesses to the bus that address the
single-cycle I/O registers (first 64 address locations).
Bit 3 – INJPDC Inject Parity Error on Data Bus Control
Write this bit to
‘1’ to inject a parity error in the data bus control on the following
data bus access. This bit is automatically cleared after one access is completed. Parity
errors will be injected only on main data bus accesses, not on accesses to the bus that
address the single-cycle I/O registers (first 64 address locations).
Bit 2 – INJPIA Inject Parity Error on Instruction Bus
Address
Write this bit to
‘1’ to inject a parity error in the address of the following instruction
fetch. This bit is automatically cleared after one fetch is completed.
Bit 1 – INJPIC Inject Parity Error on Instruction Bus
Control
Write this bit to
‘1’ to inject a parity error in the control signal of the following
instruction fetch. This bit is automatically cleared after one fetch is
completed.
Bit 0 – SPLOCK SPLIM Lock
Write this bit to
‘1’ to lock SPLIM. When SPLIM is locked it is not possible to change the
SPLIM value.
