10.7.2 Configuration Change Protection
| Name: | CCP |
| Offset: | 0x04 |
| Reset: | 0x0 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCP[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – CCP[7:0] Configuration Change Protection
Writing the correct signature to this bit field allows writing to protected I/O registers or executing protected instructions within the following four CPU instructions. During this period all interrupts are suspended, but the interrupt flags are set. After completing the period, any pending interrupts execute according to their level and priority.
After writing the protected I/O register signature, CCP[0] will read as
‘1’ as long as the CCP feature is active.
After writing the protected self-programming signature, CCP[1] will read as
‘1’ as long as the CCP feature is active.
CCP[7:2] will always read as ‘0’.
| Value | Name | Description |
|---|---|---|
| 0x9D | SPM | Allow self-programming |
| 0xD8 | IOREG | Un-protect protected I/O registers |