24.3.5 SPIn Pin Position

For available pins and functionality, refer to the I/O Multiplexing and Considerations section.

Name:	SPIROUTEA
Offset:	0x05
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
			SPI1[2:0]			SPI0[2:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 5:3 – SPI1[2:0] SPI 1 Signals

This bit field controls the pin positions for SPI 1 signals.


Value	Name	Description
Value	Name	MOSI	MISO	SCK	SS
`0x0`	DEFAULT	PC0	PC1	PC2	PC3
`0x1`	ALT1	PC4	PC5	PC6	PC7
`0x2`	ALT2	PB4⁽²⁾	Not connected⁽¹⁾	Not connected⁽¹⁾	Not connected⁽¹⁾
`0x3 - 0x6`	-	Reserved
`0x7`	NONE	Not connected to any pins			Not connected⁽¹⁾

Note:

Not connected to any pin, but the SPI logic is internally set to 1.
ALT2 is not supporting proper SPI operation, but the MOSI pin can still serve, e.g., as a digital waveform output.

Bits 2:0 – SPI0[2:0] SPI 0 Signals

This bit field controls the pin positions for SPI 0 signals.


Value	Name	Description
Value	Name	MOSI	MISO	SCK	SS
`0x0`	DEFAULT	PA4	PA5	PA6	PA7
`0x1`	ALT1	PE0	PE1	PE2	PE3
`0x2`	-	Reserved
`0x3`	ALT3	PA0	PA1	PC0	PC1
`0x4`	ALT4	PD4	PD5	PD6	PD7
`0x5`	ALT5	PC0	PC1	PC2	PC3
`0x6`	ALT6	PC1	PC2	PC3	Not connected⁽¹⁾
`0x7`	NONE	Not connected to any pins			Not connected⁽¹⁾

Note:

Not connected to any pin, but the SPI logic is set to 1 internally.

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