24.3.6 TWIn Pin Position

For available pins and functionality, refer to the I/O Multiplexing and Considerations section.

Name:	TWIROUTEA
Offset:	0x06
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
					TWI1[1:0]		TWI0[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:2 – TWI1[1:0] TWI 1 Signals

This bit field controls the pin positions for TWI 1 signals.


Value	Name	Description
		Host/Client		Dual Mode (Client)
		SDA	SCL	SDA	SCL
`0x0`	DEFAULT	PF2	PF3	PB2⁽¹⁾	PB3⁽¹⁾
`0x1`	ALT1⁽¹⁾	PF2	PF3	-	-
`0x2`	ALT2⁽¹⁾	PB2	PB3	-	-
`0x3`	-	Reserved

Note:

Only available on devices with 48 pins.

Bits 1:0 – TWI0[1:0] TWI 0 Signals

This bit field controls the pin positions for TWI 0 signals.


Value	Name	Description
		Host/Client		Dual Mode (Client)
		SDA	SCL	SDA	SCL
`0x0`	DEFAULT	PA2	PA3	PC2	PC3
`0x1`	ALT1	PA2	PA3	PC6	PC7
`0x2`	ALT2	PC2	PC3	PC6	PC7
`0x3`	ALT3	PA0	PA1	PC2	PC3

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