41.3.3.7.2 Series Accumulation

The figure below shows the timing diagram for the ADC when running in Series Accumulation mode.

Figure 41-4. Timing Diagram - Series Accumulation
Note:
  1. The time from the conversion has finished to the outputs are available in the registers is 0.5 CLK_ADC cycles followed by one CLK_MAIN cycle. With a minimum prescaler of two, this sums up to the maximum of one CLK_ADC cycle.
  2. The time from the final conversion has finished to the Result (ADCn.RESULT) register is updated is 0.5 CLK_ADC cycles followed by two CLK_MAIN cycles. With a minimum prescaler of two, this sums up to the maximum of 1.5 CLK_ADC cycles.
  3. If the Low Latency (LOWLAT) bit is set to ‘1’ in the Control A (ADCn.CTRLA) register, the analog modules in the ADC will not turn OFF at the end of the conversion, which will eliminate the initialization time when triggering the following conversion.

The number of samples to accumulate is set by the Sample Number (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register.

The total conversion time for each separate sample is calculated by:

t c o n v ⁢ = t i n i t i a l i z a t i o n + SAMPDUR + ½ + 10 + 1 f CLK_ADC