10.4.8 Data Bus Integrity

The data bus is protected by parity and redundancy:

  • The address is protected by a parity bit
  • The read data is protected by a parity bit
  • The write data is protected by a parity bit
  • The read and write strobes are duplicated and consistency checked before being used

A parity error on data received in an LD instruction will cause the destination register to be updated, but the value is UNDEFINED. The PARITYD bit in the Interrupt Flag (INTFLAGS) register is set.

A parity error on a fetched instruction will cause the PARITYI bit in the Interrupt Flag (INTFLAGS) register to be set.

Note: This corrupted instruction will be executed and lead to an undefined state in the CPU and/or the memory system. Therefore, it is necessary to enter a safe state by executing the associated NMI and/or Error Controller handling.

The PARITYD and PARITYI flags are routed to the Error Controller.

Parity error injection on the instruction and data bus can be performed using the Inject Parity Error (INJPDD, -DA, -DC, -IA, -IC) bits in the Control A (CTRLA) register.