10.4.9 Data Bus Parity Error Injection

Parity errors can be injected on the address, data and control lines of the instruction bus and data bus, as described in the Control A (CTRLA) register. The read and write strobes are protected by redundancy, so error injection on these is not possible nor needed. The error will be injected on the next bus transfer. Parity errors cannot be injected on accesses to the single-cycle I/O space, only on bus accesses to addresses above 64.

The CTRLA register is on the I/O bus, and a load/store instruction is transferred on the main data bus. The user must respect the timing differences on these buses and use a data memory barrier or similar to ensure that CTRLA has been updated with the command before the load/store arrives. In other words, ensure memory ordering.

See the BUSMATRIX - Bus Matrix section for details on the parity injection system, how the CPU and targets can inject parity errors on all bus lines, and where detected errors are reported.