10.4.15 Interrupts
| Interrupt Vector Name | Interrupt Source Name | Description | Condition |
|---|---|---|---|
| CPU | PARITYI | Parity Error on Instruction Bus detected | The Parity Error on Instruction Bus (PARITYI) flag in CPU.INTFLAGS is ‘1’ |
| PARITYD | Parity Error on Data Bus detected | The Parity Error on Data Bus (PARITYD) flag in CPU.INTFLAGS is ‘1’ | |
| SPLIM | Stack Pointer Limit Error detected | The Stack Pointer Limit Error (SPLIM) flag in CPU.INTFLAGS is ‘1’ | |
| BUSERR | Bus Error detected | The Bus Error (BUSERR) flag in CPU.INTFLAGS is ‘1’ | |
| OPC | Illegal Opcode detected | The Illegal Opcode Error (OPC) flag in CPU.INTFLAGS is ‘1’ |
The Interrupt Flags (INTFLAGS) register of the CPU is connected to the CPU Interrupt Controller (CPUINT) as Non-Maskable Interrupts (NMIs). The CPU does not have a corresponding Interrupt Control register since NMIs can, by design, not be masked or disabled. For more information about NMIs, see the CPUINT - CPU Interrupt Controller section.
Interrupt response can be prevented by writing the Global
Interrupt Enable (I) bit in the Status Register (SREG) register to ‘0’,
writing the Disable NMI Request (NMIDIS) bit in the Control A (CTRLA) register to
‘1’ and configuring the relevant Error Controller channels to severity
NOTIFICATION.
An interrupt request is generated when the corresponding interrupt flag is set. The interrupt request remains active until the interrupt flag is cleared. See the INTFLAGS register for details on how to clear interrupt flags.