10.4.1 Program Flow

After a reset, the CPU will execute instructions from the lowest address in the flash program memory, 0x0000. The instruction address on the fetch bus is masked modulo the flash size so that the instruction fetched after the instruction at the last address in the Flash will be the instruction at the first address in the Flash. In other words, the address space wraps around, making it possible to use relative jump instructions past the start and end of the Flash. Note that masking using modulo two assumes that the flash size is a power of two (2ⁿ) to work as intended.

Program flow is supported by conditional and unconditional JUMP and CALL instructions, capable of directly addressing the whole address space. Most AVR instructions use a 16-bit word format, and a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack as a word pointer. The stack is allocated in the general data SRAM, and consequently, the stack size is limited only by the total SRAM size and the usage of the SRAM. After a reset, the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The SRAM data can easily be accessed through the five different addressing modes supported by the AVR CPU. See the Instruction Set Summary section for details.