33.6.16 Command
| Name: | COMMAND |
| Offset: | 0x48 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIFF | MODE[2:0] | START[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – DIFF Differential Mode
| Value | Description |
|---|---|
| 0 | Unsigned Single-Ended conversion. Only INPUTCTRL.MUXPOS is used. |
| 1 | Signed Differential conversion. Both INPUTCTRL.MUXPOS and INPUTCTRL.MUXNEG are used. |
Bits 6:4 – MODE[2:0] Mode
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | None |
| 0x1 | SINGLE | Single conversion |
| 0x2 | SERIES | Series mode with accumulation, using a separate trigger for each conversion |
| 0x3 | BURST | Burst mode with accumulation. A single trigger will initiate the number of conversions configured by CTRLD.SAMPNUM in one sequence. |
| 0x7 | ACCTEST | Accumulator diagnostics mode |
| Other | — | Reserved |
Bits 2:0 – START[2:0] Start Conversion
Note: If CTRLA.ENABLE is ‘
0’ when this bit
field is written to IMMEDIATE, it will automatically be set to
STOP.| Value | Name | Description |
|---|---|---|
| 0x0 | STOP | Stop an ongoing conversion |
| 0x1 | IMMEDIATE | Start a conversion immediately. This bit will be reset to STOP when the conversion is complete, unless Free-Running mode is enabled. |
| 0x2 | INPUT | Start a conversion when a write to the INPUTCTRL register is performed |
| 0x4 | EVENT | Start a
conversion when an event is received by the ADC. This requires
EVCTRL.STARTEI to be set to ‘1’. |
| Other | — | Reserved |
