33.6.2 Control B

Name:	CTRLB
Offset:	0x04
Reset:	0x00000000
Property:	Local Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				TIMEBASE[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
				PRESCALER[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 12:8 – TIMEBASE[4:0] Timebase

This bit specifies the number of CLK_ADCn_APB cycles that is equivalent to or larger than 1 μs. The value must be rounded up to the closest integer. Refer to ADC Clock for details on how to calculate this.

Bits 4:0 – PRESCALER[4:0] Prescaler

This bit field controls the division factor from the peripheral clock (CLK_ADCn_APB) to the ADC clock (CLK_ADC).

Value	Name	Description
0x00	DIV2	APB clock divided by 2
0x01	DIV3	APB clock divided by 3
0x02	DIV4	APB clock divided by 4
0x03	DIV5	APB clock divided by 5
0x04	DIV6	APB clock divided by 6
0x05	DIV7	APB clock divided by 7
0x06	DIV8	APB clock divided by 8
0x07	DIV9	APB clock divided by 9
0x08	DIV10	APB clock divided by 10
0x09	DIV11	APB clock divided by 11
0x0A	DIV12	APB clock divided by 12
0x0B	DIV13	APB clock divided by 13
0x0C	DIV14	APB clock divided by 14
0x0D	DIV15	APB clock divided by 15
0x0E	DIV16	APB clock divided by 16
0x0F	DIV17	APB clock divided by 17
0x10	DIV18	APB clock divided by 18
0x11	DIV19	APB clock divided by 19
0x12	DIV20	APB clock divided by 20
0x13	DIV21	APB clock divided by 21
0x14	DIV22	APB clock divided by 22
0x15	DIV23	APB clock divided by 23
0x16	DIV24	APB clock divided by 24
0x17	DIV25	APB clock divided by 25
0x18	DIV26	APB clock divided by 26
0x19	DIV27	APB clock divided by 27
0x1A	DIV28	APB clock divided by 28
0x1B	DIV29	APB clock divided by 29
0x1C	DIV30	APB clock divided by 30
0x1D	DIV31	APB clock divided by 31
0x1E	DIV32	APB clock divided by 32
Other	—	Reserved