33.6.4 Control D
| Name: | CTRLD |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VPD | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FILTER | CHOPPING | FREERUN | SCALING[1:0] | RESOLUTION[1:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMPNUM[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 16 – VPD Voltage Pump Disable
| Value | Description |
|---|---|
| 0 | Voltage pump is enabled |
| 1 | Voltage pump is disabled |
Bit 14 – FILTER Low-Pass Filter
This bit enables the low-pass filter. It is only used in Series and Burst modes.
| Value | Description |
|---|---|
| 0 | Low-pass filter is disabled |
| 1 | Low-pass filter is enabled |
Bit 13 – CHOPPING Sign Chopping
This bit controls whether sign chopping is enabled to reduce offset.
It is only used in Series and Burst modes.
| Value | Description |
|---|---|
| 0 | Sign chopping is disabled |
| 1 | Sign chopping is enabled |
Bit 12 – FREERUN Free-Running
This bit controls whether the ADC Free-Running mode is enabled.
| Value | Description |
|---|---|
| 0 | The ADC Free-Running mode is disabled |
| 1 | The ADC Free-Running mode is enabled. A new conversion starts as soon as the previous conversion or accumulation is completed, as indicated by INTFLAG.RESRDY. |
Bits 11:10 – SCALING[1:0] Result Scaling
This bitfield controls the scaling of the digital value in SAMPLE and RESULT registers. In NORMAL mode, the full accumulated result is returned. In LEFTADJ mode, the result is truncated if it exceeds 16 bits. In AVERAGE mode, the result is rounded to the configured resolution.
| Value | Name | Description |
|---|---|---|
| 0x0 | NORMAL | The ADC output of the sample or accumulated result is right adjusted |
| 0x1 | LEFTADJ | The ADC output is left adjusted |
| 0x2 | AVERAGE | The accumulated ADC result is averaged and right adjusted |
| Other | — | Reserved |
Bits 9:8 – RESOLUTION[1:0] ADC Resolution
This bit-field defines the number of bits output from the ADC after a conversion. The conversion time depends on the number of bits.
| Value | Name | Description |
|---|---|---|
| 0x0 | 12BIT | 12-bit ADC Result |
| 0x1 | 13BIT | 13-bit ADC Result |
| 0x2 | 10BIT | 10-bit ADC Result |
| 0x3 | 8BIT | 8-bit ADC Result |
Bits 3:0 – SAMPNUM[3:0] Sample Accumulation Number Select
This bit field controls the number of consecutive ADC samples that are automatically accumulated into the ADC Result (ADCn.RESULT) register. The most recent sample will be available in the ADC Sample (ADCn.SAMPLE) register.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | No accumulation, single sample per conversion result |
| 0x1 | ACC2 | 2 samples accumulated |
| 0x2 | ACC4 | 4 samples accumulated |
| 0x3 | ACC8 | 8 samples accumulated |
| 0x4 | ACC16 | 16 samples accumulated |
| 0x5 | ACC32 | 32 samples accumulated |
| 0x6 | ACC64 | 64 samples accumulated |
| 0x7 | ACC128 | 128 samples accumulated |
| 0x8 | ACC256 | 256 samples accumulated |
| 0x9 | ACC512 | 512 samples accumulated |
| 0xA | ACC1024 | 1024 samples accumulated |
| Other | — | Reserved |