33.6.1 Control A


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	ONDEMAND	RUNSTDBY					ENABLE	SWRST
Access	R/W	R/W					R/W	W
Reset	0	0					0	0

Bit 7 – ONDEMAND On Demand

This bit controls whether the required analog modules remain enabled.

Note: ONDEMAND does not keep the clock source enabled when the ADC is not converting, so a clock startup delay may occur even if ONDEMAND is cleared. To avoid this delay, ensure that the clock source is always enabled.

Value	Description
0	The analog modules remain enabled as long as they are selected as input to the ADC. This configuration minimizes the ADC initialization time.
1	The ADC enables the required analog modules only when starting a conversion. This reduces overall power consumption but increases the initialization time when starting an ADC conversion.

Bit 6 – RUNSTDBY Run in Standby

This bit controls whether the ADC operates in Standby sleep mode.

Value	Description
0	The ADC will not operate in Standby sleep mode. An ongoing conversion will complete before the ADC enters sleep mode.
1	The ADC will operate in Standby sleep mode. The main clock will be requested when the ADC is triggered to perform a conversion.

Bit 1 – ENABLE ADC Enable

This bit controls whether the ADC is enabled.

Value	Description
0	The ADC is disabled
1	The ADC is enabled

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the ADC, except the Debug Control (DBGCTRL) register, to their initial state, and disables the ADC.

Note: Writing a ‘1’ to CTRLA.SWRST will always take precedence; all other writes in the same write operation will be discarded.

Value	Description
0	No effect
1	All registers in the ADC, except DBGCTRL, are reset to their initial state, and the ADC is disabled

Name:	CTRLA
Offset:	0x00
Reset:	0x00000000
Property:	Local Write-Protection