33.6.11 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRIGOVR | SAMPOVR | RESOVR | WCMP | SAMPRDY | RESRDY | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – TRIGOVR Trigger Overrun Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Trigger Overrun Interrupt
Enable bit, disabling the trigger overrun interrupt.
| Value | Description |
|---|---|
| 0 | The Trigger Overrun interrupt is disabled |
| 1 | The Trigger Overrun interrupt is enabled |
Bit 4 – SAMPOVR Sample Overwrite Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Sample Overwrite Interrupt
Enable bit, disabling the sample overwrite interrupt.
| Value | Description |
|---|---|
| 0 | The Sample Overwrite interrupt is disabled |
| 1 | The Sample Overwrite interrupt is enabled |
Bit 3 – RESOVR Result Overwrite Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Result Overwrite Interrupt
Enable bit, disabling the result overwrite interrupt.
| Value | Description |
|---|---|
| 0 | The Result Overwrite interrupt is disabled |
| 1 | The Result Overwrite interrupt is enabled |
Bit 2 – WCMP Window Comparator Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Window Comparator Interrupt
Enable bit, disabling the window comparator interrupt.
| Value | Description |
|---|---|
| 0 | The Window Comparator interrupt is disabled |
| 1 | The Window Comparator interrupt is enabled |
Bit 1 – SAMPRDY Sample Ready Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Sample Ready Interrupt
Enable bit, disabling the sample ready interrupt.
| Value | Description |
|---|---|
| 0 | The Sample Ready interrupt is disabled |
| 1 | The Sample Ready interrupt is enabled |
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Result Ready Interrupt
Enable bit, disabling the result ready interrupt.
| Value | Description |
|---|---|
| 0 | The Result Ready interrupt is disabled |
| 1 | The Result Ready interrupt is enabled |