27.6.5 Data Output Value

This register controls the output drive for the individual I/O pins in the PORT.

This register can be manipulated without performing a Read-Modify-Write (RMW) operation by using the Data Output Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers.

Name:	OUT
Offset:	0x10
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	OUT31	OUT30	OUT29	OUT28	OUT27	OUT26	OUT25	OUT24
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	OUT23	OUT22	OUT21	OUT20	OUT19	OUT18	OUT17	OUT16
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	OUT15	OUT14	OUT13	OUT12	OUT11	OUT10	OUT9	OUT8
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	OUT7	OUT6	OUT5	OUT4	OUT3	OUT2	OUT1	OUT0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – OUTn PORT Data Output Value n

For pins configured as outputs through the Data Direction register (DIR), these bits set the logical output drive level.

For pins configured as inputs through the DIR register and with pull enabled through the Pull Enable bit in the Pin Configuration register (PINCFG.PULLEN), these bits configure the input pull direction.

Value	Description
0	The pin in the PORT group corresponding to this bit is driven low
1	The pin in the PORT group corresponding to this bit is driven high, or the input is connected to an internal pull-up