27.6.3 Data Direction Set

This register allows the user to set one or more I/O pins as outputs, without performing a Read-Modify-Write (RMW) operation on the Data Direction register (DIR). Changes in this register will be reflected in the DIR, Data Direction Toggle (DIRTGL), and Data Direction Clear (DIRCLR) registers.

Name:	DIRSET
Offset:	0x08
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	DIR31SET	DIR30SET	DIR29SET	DIR28SET	DIR27SET	DIR26SET	DIR25SET	DIR24SET
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DIR23SET	DIR22SET	DIR21SET	DIR20SET	DIR19SET	DIR18SET	DIR17SET	DIR16SET
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DIR15SET	DIR14SET	DIR13SET	DIR12SET	DIR11SET	DIR10SET	DIR9SET	DIR8SET
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DIR7SET	DIR6SET	DIR5SET	DIR4SET	DIR3SET	DIR2SET	DIR1SET	DIR0SET
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DIRnSET Port Data Direction n Set

Writing a ‘0’ to a bit has no effect.

Writing a ‘1’ to a bit will set the corresponding bit in the DIR register, which configures the I/O pin as an output.

Value	Description
0	The I/O pin in the PORT group corresponding to this bit is configured as an input
1	The I/O pin in the PORT group corresponding to this bit is configured as an output