27.6.1 Data Direction

This register allows the user to configure one or more I/O pins as an input or output.

This register can be manipulated without performing a Read-Modify-Write (RMW) operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear (DIRCLR), and Data Direction Set (DIRSET) registers.

Name:	DIR
Offset:	0x00
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	DIR31	DIR30	DIR29	DIR28	DIR27	DIR26	DIR25	DIR24
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DIR23	DIR22	DIR21	DIR20	DIR19	DIR18	DIR17	DIR16
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DIR15	DIR14	DIR13	DIR12	DIR11	DIR10	DIR9	DIR8
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DIR7	DIR6	DIR5	DIR4	DIR3	DIR2	DIR1	DIR0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DIRn Port Data Direction n

These bits control the data direction for the individual I/O pins in the PORT group.

Value	Description
0	The I/O pin in the PORT group corresponding to this bit is configured as an input
1	The I/O pin in the PORT group corresponding to this bit is configured as an output