27.6.2 Data Direction Clear

This register allows the user to set one or more I/O pins as inputs, without performing a Read-Modify-Write (RMW) operation on the Data Direction register (DIR). Changes in this register will be reflected in the DIR, Data Direction Toggle (DIRTGL), and Data Direction Set (DIRSET) registers.

Name:	DIRCLR
Offset:	0x04
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	DIR31CLR	DIR30CLR	DIR29CLR	DIR28CLR	DIR27CLR	DIR26CLR	DIR25CLR	DIR24CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DIR23CLR	DIR22CLR	DIR21CLR	DIR20CLR	DIR19CLR	DIR18CLR	DIR17CLR	DIR16CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DIR15CLR	DIR14CLR	DIR13CLR	DIR12CLR	DIR11CLR	DIR10CLR	DIR9CLR	DIR8CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DIR7CLR	DIR6CLR	DIR5CLR	DIR4CLR	DIR3CLR	DIR2CLR	DIR1CLR	DIR0CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DIRnCLR Port Data Direction n Clear

Writing a ‘0’ to a bit has no effect.

Writing a ‘1’ to a bit will clear the corresponding bit in the DIR register, which configures the I/O pin as an input.

Value	Description
0	The I/O pin in the PORT group corresponding to this bit is configured as an input
1	The I/O pin in the PORT group corresponding to this bit is configured as an output