27.6.6 Data Output Value Clear

This register allows the user to set the low drive level for one or more output I/O pins, without performing a Read-Modify-Write (RMW) operation on the Data Output Value register (OUT). Changes in this register will be reflected in the OUT, Data Output Value Toggle (OUTTGL), and Data Output Value Set (OUTSET) registers.

Name:	OUTCLR
Offset:	0x14
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	OUT31CLR	OUT30CLR	OUT29CLR	OUT28CLR	OUT27CLR	OUT26CLR	OUT25CLR	OUT24CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	OUT23CLR	OUT22CLR	OUT21CLR	OUT20CLR	OUT19CLR	OUT18CLR	OUT17CLR	OUT16CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	OUT15CLR	OUT14CLR	OUT13CLR	OUT12CLR	OUT11CLR	OUT10CLR	OUT9CLR	OUT8CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	OUT7CLR	OUT6CLR	OUT5CLR	OUT4CLR	OUT3CLR	OUT2CLR	OUT1CLR	OUT0CLR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – OUTnCLR PORT Data Output Value n Clear

Writing a ‘0’ to a bit has no effect.

Writing a ‘1’ to a bit will clear the corresponding bit in the OUT register.

Value	Description
0	The pin in the PORT group corresponding to this bit is driven low
1	The pin in the PORT group corresponding to this bit is driven high, or the input is connected to an internal pull-up