27.6.14 Pin Configuration n
| Name: | PINCFG[n] |
| Offset: | 0x40 + n*0x01 [n=0..31] |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLEWLIM | PULLEN | INEN | PMUXEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 4 – SLEWLIM Output Driver Slew Rate Limit Enable
| Value | Description |
|---|---|
| 0 | Output Driver Slew Rate Limit is disabled |
| 1 | Output Driver Slew Rate Limit is enabled |
Bit 2 – PULLEN Pull Enable
| Value | Description |
|---|---|
| 0 | The internal pull resistor is disabled, and the input is in a high-impedance configuration |
| 1 | The internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of external input |
Bit 1 – INEN Input Buffer Enable
This bit controls the input buffer of an I/O pin configured as either an input or output.
Writing a ‘0’ to this bit disables the input buffer completely, preventing read-back of the physical pin state when the pin is configured as either an input or output.
| Value | Description |
|---|---|
| 0 | The input buffer for the I/O pin is disabled, and the input value will not be sampled |
| 1 | The input buffer for the I/O pin is enabled, and the input value will be sampled when required |
Bit 0 – PMUXEN Peripheral Multiplexer Enable
This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUX[m]), allowing alternative peripheral control over an I/O pin's direction and output drive value.
Writing a ‘0’ to this bit allows the PORT to control the pad direction through the Data Direction register (DIR) and the output drive value through the Data Output Value register (OUT). The peripheral multiplexer value in PMUX[m] is ignored.
Writing a ‘1’ to this bit enables the peripheral selection in PMUX[m] to control the pad. In this configuration, the physical pin state can still be read from the Data Input Value register (IN) if PINCFG[n].INEN is ‘1’.
| Value | Description |
|---|---|
| 0 | The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive value |
| 1 | The peripheral multiplexer selection is enabled, and the selected peripheral function controls the direction and output drive value |