27.6.4 Data Direction Toggle
| Name: | DIRTGL |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DIR31TGL | DIR30TGL | DIR29TGL | DIR28TGL | DIR27TGL | DIR26TGL | DIR25TGL | DIR24TGL | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DIR23TGL | DIR22TGL | DIR21TGL | DIR20TGL | DIR19TGL | DIR18TGL | DIR17TGL | DIR16TGL | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIR15TGL | DIR14TGL | DIR13TGL | DIR12TGL | DIR11TGL | DIR10TGL | DIR9TGL | DIR8TGL | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIR7TGL | DIR6TGL | DIR5TGL | DIR4TGL | DIR3TGL | DIR2TGL | DIR1TGL | DIR0TGL | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DIRnTGL Port Data Direction n Toggle
Writing a ‘0’ to a bit has no effect.
Writing a ‘1’ to a bit will toggle the corresponding bit in the DIR register, which reverses the direction of the I/O pin.
| Value | Description |
|---|---|
| 0 | The I/O pin in the PORT group corresponding to this bit is configured as an input |
| 1 | The I/O pin in the PORT group corresponding to this bit is configured as an output |
