27.6.11 Write Configuration

This write-only register is used to configure several pins simultaneously with the same configuration and peripheral multiplexing.

To avoid side effect from non-atomic access, 8- or 16-bit writes to this register will have no effect.

Reading this register always returns ‘0’.

Name: WRCONFIG
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 HWSELWRPINCFG WRPMUXPMUX[3:0] 
Access WWWWWWW 
Reset 0000000 
Bit 2322212019181716 
    SLEWLIM PULLENINENPMUXEN 
Access WWWW 
Reset 0000 
Bit 15141312111098 
 PINMASK[15:8] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 PINMASK[7:0] 
Access WWWWWWWW 
Reset 00000000 

Bit 31 – HWSEL Half-Word Select

This bit selects the half-word field of a 32-pin PORT group to be reconfigured in the atomic write operation.

ValueDescription
0The lower 16 pins of the PORT group will be configured
1The upper 16 pins of the PORT group will be configured

Bit 30 – WRPINCFG Write PINCFG

This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFG[n]) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit updates the configuration of the selected pins with the values written toWRCONFIG.SLEWLIM, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.

Bit 28 – WRPMUX Write PMUX

This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUX[m]) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG.PMUX value.

Bits 27:24 – PMUX[3:0] Peripheral Multiplexing

These bits determine the new value written to the Peripheral Multiplexing for Odd-Numbered Pin (PMUX[m].PMUXO) or Peripheral Multiplexing for Even-Numbered Pin (PMUX[m].PMUXE) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.

ValueNameDescription
0x00APeripheral function A selected
0x01BPeripheral function B selected
0x02CPeripheral function C selected
0x03DPeripheral function D selected
0x04EPeripheral function E selected
0x05FPeripheral function F selected
0x06GPeripheral function G selected
0x07HPeripheral function H selected
0x08IPeripheral function I selected
0x09JPeripheral function J selected
Other—Reserved

Bit 20 – SLEWLIM Output Driver Slew Rate Limit Enable

This bit determines the new value written to the PINCFG[n].SLEWLIM for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
ValueDescription
0Output Driver Slew Rate Limit is disabled
1Output Driver Slew Rate Limit is enabled

Bit 18 – PULLEN Pull Enable

This bit determines the new value written to the PINCFG[n].PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
ValueDescription
0The internal pull resistor is disabled, and the input is in a high-impedance configuration
1The internal pull resistor is enabled, and the input is driven to a defined logic level in the absence of external input

Bit 17 – INEN Input Enable

This bit determines the new value written to the PINCFG[n].INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
ValueDescription
0The input buffer for the I/O pin is disabled, and the input value will not be sampled
1The input buffer for the I/O pin is enabled, and the input value will be sampled when required

Bit 16 – PMUXEN Peripheral Multiplexer Enable

This bit determines the new value written to the PINCFG[n].PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
ValueDescription
0The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive value
1The peripheral multiplexer selection is enabled, and the selected peripheral function controls the direction and output drive value

Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration

These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.

Writing a ‘0’ to a bit has no effect.

Writing a ‘1’ to a bit will update the configuration of the corresponding I/O pin in the half-word PORT group.