1.3.2.2.1 PF_PCIE_0
(Ask a Question)The PF_PCIE_0 IP block is used to configure the PCIESS as a Root Port (PCIe 1). PCIESS block is configured for × 4 lanes, 5 Gbps data rate, and APB interface for PCIe Controller access.
The PF_PCIE_0 IP block is used to configure the PCIESS as a Root Port (PCIe 1). PCIESS block is configured for × 4 lanes, 5 Gbps data rate, and APB interface for PCIe Controller access.
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