1.3.2.2.3 PCIe_TL_CLK_0 SmartDesign
(Ask a Question)The following figure shows the PCIe_TL_CLK SmartDesign implementing PCIe TL CLK for PolarFire devices. PCIe TL CLK must be connected to CLK_125 MHz of Tx PLL. In PolarFire devices, TL CLK is available only after PCIe initialization. The 80 MHz clock is derived from the on-chip 160 MHz oscillator to drive the TL CLK during PCIe initialization. The NGMUX is used to switch this clock to the required CLK_125 MHz after PCIe initialization.
